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semiconductor group 1 4.96 4m x 1-bit dynamic ram low power 4m x 1-bit dynamic ram a dvanced information ? 4 194 304 words by 1-bit organization ? 0 to 70 ?c operating temperature ? fast page mode operation ? performance: ? single + 3.3 v ( 0.3 v ) supply with a built-in v bb generator ? low power dissipation max. 252 mw active (-50 version) max. 216 mw active (-60 version) max. 198 mw active (-70 version) ? standby power dissipation: 7.2 mw max. standby (ttl) 3.6 mw max. standby (cmos) 720 m w max. standby (cmos) for low power version ? output unlatched at cycle end allows two-dimensional chip selection ? read, write, read-modify write, cas-before- ras refresh, ras-only refresh, hidden refresh and test mode capability ? all inputs and outputs ttl-compatible ? 1024 refresh cycles / 16 ms ? 1024 refresh cycles / 128 ms low power version ? plastic packages: p-soj-26/20-5 with 300 mil width -50 -60 -70 t rac ras access time 50 60 70 ns t cac cas access time 13 15 20 ns t aa access time from address 25 30 35 ns t rc read/write cycle time 95 110 130 ns t pc fast page mode cycle time 35 40 45 ns hyb 314100bj/bjl -50/-60/-70
semiconductor group 2 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram the hyb 314100bj/bjl is the new generation dynamic ram organized as 4 194 304 words by 1-bit. the hyb 314100bj/bjl utilizes cmos silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. multiplexed address inputs permit the hyb 514100bj/bjl to be packed in a standard plastic p-soj-26/20 package. this package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. system oriented features include single + 3.3 v ( 0.3 v) power supply, direct interfacing with high performance logic device families. ordering information type ordering code package descriptions hyb 314100bj-50 q67100-q2035 p-soj-26/20-5 3.3 v dram (access time 50 ns) hyb 314100bj-60 q67100-q2037 p-soj-26/20-5 3.3 v dram (access time 60 ns) hyb 314100bj-70 q67100-q2039 p-soj-26/20-5 3.3 v dram (access time 70 ns) hyb 314100bjl-50 on request p-soj-26/20-5 3.3 v low power dram (access time 50 ns) hyb 314100bjl-60 on request p-soj-26/20-5 3.3 v low power dram (access time 60 ns) hyb 314100bjl-70 on request p-soj-26/20-5 3.3 v low power dram (access time 70 ns)
semiconductor group 3 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram pin configuration (top view) pin names a0-a10 address input ras row address strobe cas column address strobe we read/write input di data in do data out v cc power supply (+ 3.3 v) v ss ground (0 v) n.c. no connection p-soj-26/20-5
semiconductor group 4 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram block diagram
semiconductor group 5 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram absolute maximum ratings operating temperature range ............................................................................................0 to 70 ?c storage temperature range......................................................................................C 55 to + 150 ?c input/output voltage ........................................................................... C 1 to + min ( v cc + 0.5, 4.6) v power supply voltage .................................................................................................. C 1 to + 4.6 v data out current (short circuit) ................................................................................................ 50 ma note: stresses above those listed under "absolute maximum ratings" may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 ?c, v ss = 0 v, v cc = 3.3 v 0.3 v , t t = 5 ns parameter symbol limit values unit test condition min. max. input high voltage v ih 2.0 v cc + 0.5 v 1) input low voltage v il C 1.0 0.8 v 1) ttl output high voltage ( i out = C 2 ma) v oh 2.4 C v 1) ttl output low voltage ( i out = 2 ma) v ol C 0.4 v 1) cmos output high voltage ( i out = C 100 m a) v oh v cc C 0.2 C v cmos output low voltage ( i out = 100 m a ) v ol C 0.2 v input leakage current, any input (0 v < v in < v cc + 0.3 v, all other input = 0 v) i i(l) C 10 10 m a 1) output leakage current (do is disabled, 0 v < v out < v cc ) i o(l) C 10 10 m a 1) average v cc supply current -50 version -60 version -70 version i cc1 _ C C 70 60 55 ma 2) 3)4) standby v cc supply current ( ras = cas = we = v ih ) i cc2 C2maC average v cc supply current during ras-only refresh cycles -50 version -60 version -70 version i cc3 _ C C 70 60 55 ma 2)4) average v cc supply current during fast page mode operation -50 version -60 version -70 version i cc4 C C 50 45 40 ma 2) 3)4) standby v cc supply current ( ras = cas = we = v cc C 0.2 v) i cc5 C1 200 ma m a 1) l-version
semiconductor group 6 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram average v cc supply current during cas before ras refresh mode -50 version -60 version -70 version i cc6 C C C 70 60 55 ma 2)4) for low power version only: battery backup current (average power supply current in battery backup mode): ( cas = cas before ras cycling or 0.2 v, we = v cc C 0.2 v or 0.2 v, a0 to a10 = v cc C 0.2 v or 0.2 v; d i = v cc C 0.2 v or 0.2 v or open, t rc = 125 m s, t ras = t ras min = 1 m s) i cc7 C 250 m aC capacitance t a = 0 to 70 ?c; v cc = 3.3 v 0.3 v; f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a10, di) c i1 C5pf input capacitance ( ras, cas, we) c i2 C7pf output capacitance (do) c io C7pf dc characteristics (contd) t a = 0 to 70 ?c, v ss = 0 v, v cc = 3.3 v 0.3 v , t t = 5 ns parameter symbol limit values unit test condition min. max.
semiconductor group 7 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram ac characteristics 5)6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max. common parameters random read or write cycle time t rc 95 C 110 C 130 C ns ras precharge time t rp 35 C 40 C 50 C ns ras pulse width t ras 50 10k 60 10k 70 10k ns cas pulse width t cas 13 10k 15 10k 20 10k ns row address setup time t asr 0C0C0Cns row address hold time t rah 8C10C10Cns column address setup time t asc 0C0C0Cns column address hold time t cah 10 C 15 C 15 C ns ras to cas delay time t rcd 18 37 20 45 20 50 ns ras to column address delay time t rad 13 25 15 30 15 35 ns ras hold time t rsh 13 15 C 20 C ns cas hold time t csh 50 60 C 70 C ns cas to ras precharge time t crp 5C5C5Cns transition time (rise and fall) t t 350350350ns7 refresh period t ref C16C16C16ms refresh period for l-version t ref C 128 C 128 C 128 ms read cycle access time from ras t rac C 50 C 60 C 70 ns 8, 9 access time from cas t cac C 13 C 15 C 20 ns 8, 9 access time from column address t aa C 25 C 30 C 35 ns 8,10 column addr. to ras lead time t ral 25 C 30 C 35 C ns read command setup time t rcs 0C0C0Cns read command hold time t rch 0C0C0Cns11 read command hold time referenced to ras t rrh 0C0C0Cns11 cas to output in low-z t clz 0C0C0Cns8
semiconductor group 8 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram output buffer turn-off delay t off 013015020ns12 write cycle write command hold time t wch 8C10C10Cns write command pulse width t wp 8C10C10Cns write command setup time t wcs 0C0C0Cns13 write command to ras lead time t rwl 13 C 15 C 20 C ns write command to cas lead time t cwl 13 C 15 C 20 C ns data setup time t ds 0C0C0Cns14 data hold time t dh 10 C 10 C 15 C ns 14 read-modify-write cycle read-write cycle time t rwc 115 C 130 C 155 C ns ras to we delay time t rwd 50 C 60 C 70 C ns 13 cas to we delay time t cwd 13 C 15 C 20 C ns 13 column address to we delay time t awd 25 C 30 C 35 C ns 13 fast page mode cycle fast page mode cycle time t pc 35 C 40 C 45 C ns cas precharge time t cp 10 C 10 C 10 C ns access time from cas precharge t cpa C30C35C40ns7 ras pulse width t ras 50 200 k 60 200 k 70 200 k ns cas precharge to ras delay t rhcp 30 C 35 C 40 C ns ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 9 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram fast page mode read-modify-write cycle fast page mode read-write cycle time t prwc 55 C 60 C 70 C ns cas precharge to we t cpwd 30 C 35 C 40 C ns cas-before- ras refresh cycle cas setup time t csr 10 C 10 C 10 C ns cas hold time t chr 10 C 10 C 10 C ns ras to cas precharge time t rpc 5C5C5Cns write to ras precharge time t wrp 10 C 10 C 10 C ns write hold time referenced to ras t wrh 10 C 10 C 10 C ns cas-before- ras counter test cycle cas precharge time t cpt 35 C 40 C 40 C ns test mode write command setup time t wts 10 C 10 C 10 C ns write command hold time t wth 10 C 10 C 10 C ns ac characteristics (contd) 5)6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3 v, t t = 5 ns parameter symbol limit values unit note -50 -60 -70 min. max. min. max. min. max.
semiconductor group 10 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram notes: 1) all voltages are referenced to v ss . 2) i cc1 , i cc3 , i cc4 and i cc6 depend on cycle rate. 3) i cc1 and i cc4 depend on output loading. specified values are measured with the output open. 4) address can be changed once or less while ras = v il . in the case of i cc4 it can be changed once or less during a fast page mode cycle ( t pc ). 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas-before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume t t = 5 ns. 7) v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 8) measured with the specified current load and 100 pf at v ol = 0.8 and v oh = 2.0 v. 9) operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only: if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10)operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only: if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t aa . 11)either t rch or t rrh must be satisfied for a read cycle. 12) t off (max.) defines the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and the data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) , t awd > t awd (min.) and t cpwd > t cpwd (min.) , the cycle is a read-write cycle and do will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the do pin (at access time) is indeterminate. 14)these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read-write cycles.
semiconductor group 11 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram read cycle
semiconductor group 12 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram write cycle (early write)
semiconductor group 13 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram read-write (read-modify-write) cycle
semiconductor group 14 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram fast page mode read-modify-write cycle
semiconductor group 15 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram fast page mode read cycle
semiconductor group 16 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram fast page mode early write cycle
semiconductor group 17 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram ras-only refresh cycle
semiconductor group 18 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram cas-before- ras refresh cycle
semiconductor group 19 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram hidden refresh cycle (read)
semiconductor group 20 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram hidden refresh cycle (early write)
semiconductor group 21 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram cas-before- ras refresh counter test cycle
semiconductor group 22 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram test mode entry test mode the hyb314100bj/bjl is organized 4 194 304 words by 1- bit but can internally be configured as 524 288 words by 8-bits. a we, cas-before- ras cycle puts the device into test mode. in test mode, data is written into 8 sectors in parallel and retrieved the same way. if, upon reading, all bits are equal, the data output pin indicates a 1. if any of the bits differ, the data output pin indicates a 0. in test mode the 4m dram can be tested as if it were a 512k dram. test mode is exited by any refresh operation which is not a we, cas- before- ras cycle. addresses a10r, a10c and a0c do not care during test mode.
semiconductor group 23 hyb 314100bj/bjl-50/-60/-70 3.3v 4m x 1 dram package outlines plastic package p-soj-26/20-5 (plastic small outline j-leaded package) gpj05627 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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